The present invention relates in general to integrated digital circuits, and more particularly, to a voltage regulator for a charge pump generating a high voltage (HV) starting from the supply voltage of the integrated circuit.
In EEPROM memory devices it is necessary to keep the high voltage, generated by the charge pump for programming and erasing operations (12-15 V), as constant as possible independently of the required driving capability, which is on the order of tens of xcexcA. It is important that a certain and stable output voltage Vout be produced to ensure that it will not surpass the limit imposed by the dielectric strength of oxides of transistor structures, as well as of capacitors, to prevent the risk of permanently damaging them.
The basic diagram of FIG. 1 illustrates a commonly implemented regulator. A desired Vreg (regulation voltage) is generated inside the integrated device, based on a known and very stable voltage reference (BandGap circuit), and is input to a comparator that compares it with the output voltage Vout of the charge pump.
When Vout greater than Vreg, the regulator sends a logic signal VON to a control circuit that stops the application of clock pulses to the phase generator. As a consequence, the charge pump starts to discharge, and as soon as Vout less than Vreg, the regulator re-enables the driving action of the clock on the phase generator.
With this feedback, a dynamic equilibrium at the steady state condition Vout=Vreg is eventually reached. In a loadless condition, the charge pump is practically turned off, with the evident advantage (especially for minimizing power consumption) of not wasting power. When a load absorbs current, the regulator enables clock pulses to drive the charge pump at a frequency f0 sufficient for precisely compensating the drop of Vout because of the delivering of an electrical charge.
The current-voltage characteristic of an N stage pump of capacitance C, supplied at the supply voltage Vdd and regulated with a frequency f0xe2x89xa6fmax is shown in FIG. 2. The charge pump generates a constant output voltage Vout=Vreg for any load current, up to the current I0,max compatible with that voltage.
When the load absorbs a certain current I0, the regulator adjusts the frequency of the clock pulses that reach the phase generator in the neighborhood of a frequency f0 smaller than fmax, making the pump work at the operating point (Vout=Vreg, Iout=I0). In practice, it is as if the slope of the load line had been modified to determine the appropriate output resistance Rout.
The ideal characteristic of FIG. 2 satisfies the following equation:       I    out    =            fC      N        ⁢          (                                    (                          N              +              1                        )                    ⁢                      V            dd                          -                  V          out                    )      
FIG. 3 shows a commonly used regulator circuit. The circuit uses a resistive voltage divider by which a certain fraction VR of the output voltage Vout is tapped and compared by a comparator with the reference voltage VBG usually produced by a bandgap circuit. The output VON of the comparator is a logic signal that enables or disables the passage of clock pulses from the oscillator to the phase generator. Moreover, a properly dimensioned capacitive network is connected in parallel to the voltage divider for reasons that will be explained in the following paragraph.
The regulated voltage (in terms of mean value) is equal to:       V    out    =            V      BG        ⁡          (              1        +                              R            UP                                R            DOWN                              )      
The precision of the regulator is tied essentially to the speed with which the node VR responds to voltage variations of Vout for restoring the condition VR=VBG. If the resistors were ideal, the response would be instantaneous. In reality, the variation of Vout propagates to the input of the comparator only after the voltage on the parasitic (distributed) capacitances associated with the integrated resistors have changed, and this slows down the response of the regulation loop.
In order to compensate this effect, a capacitor CUP is introduced between the node Vout and the node VR, the size of which is chosen based upon a simulated step response, as depicted in FIG. 4. With only the resistive line, the voltage VR increases quite slowly following a sub-compensated characteristic (curve a). Taking into consideration possible uncontrollable variations of parameters, instead of compensating exactly, it is often preferable to overcompensate, in order to benefit from an enhanced reactivity of the control loop.
To avoid an undershoot (curve b) that would imply an overshoot of the regulated voltage (because the comparator would consider the interval in which VR less than VBG as an absence of regulation, thus letting clock pulses reach the phase generator and thus increasing the HVP level), the value of CUP is increased until the undershoot becomes null (curve c). Finally, for reducing the over-elongation peak that could cause spurious switching of the comparator, a capacitor CDOWN, about four times greater than CUP, is used (curve d).
This common regulation system is subject to dynamic problems. The more frequently the regulator must intervene (that is, the higher is the current required to be delivered by the charge pump), less readily the voltage VR follows the variations of the output voltage Vout. In other words, the response of the regulation loop becomes slower as the load current increases, and any inaccuracy of regulation in terms of an offset (difference) VRxe2x88x92VBG present at the input of the comparator implies an error on Vout that is equal to the offset itself amplified by the ratio RUP/RDOWN, and it may even be on the order of hundreds of mVs.
With modern technologies, this problem becomes even more severe. The reduced value of the bandgap voltage (xcx9c840 mV versus xcx9c1.38 V for older technologies), coupled to a high value of RUP (for reducing current consumption through the voltage divider), renders even more difficult accurate regulation of the voltage Vout, and indeed errors of up to 300-400 mV are not infrequent.
In view of the foregoing background, the purpose of the present invention is to overcome the above described difficulties.
The objective has been fully achieved by adopting an innovative technique that includes comparing the reference bandgap voltage not only with the instantaneous value of VR, as it is normally done, but also with a filtered replica thereof obtained by the use of an RC low-pass filter. In this way, even the average value of VR, hereinafter called VRfilter, is accounted for compensating an eventual offset that may be present and that, as we have seen in the known circuits, causes a magnified error on the regulated voltage (normally the magnifying ratio RUP/RDOWNis about 12).
An objective is thus to provide a regulator for a HV charge pump, capable of self adapting itself to the varying level of the load current, compensating the variation of the regulating effect that normally occurs between extreme operating conditions (that is, near a null load and the maximum load).
According to the present invention, a regulator of the output voltage of a charge pump operates through the whole range of variation of the current absorbed by the load of the charge pump The regulator comprises a voltage divider for the output voltage of the charge pump for tapping a certain fraction of the output voltage, and a comparator for comparing the tapped voltage fraction with a constant reference voltage applied to respective inputs of the comparator and outputting a resultant digital signal. A logic control circuit is input with a main clock signal and outputs a timing signal, the frequency of which is determined by the state of the digital signal at every pulse of the main clock signal. A circuit generates control phases of the charge pump as a function of the timing signal.
The regulator is characterized in that it further comprises a low-pass filter for the output voltage fraction, the time constant of which is automatically switched at least between two pre-established values as a function of a certain control signal generated by an integrating circuit to an input of which an inverted replica of the digital signal generated by the comparator is applied. The filtered voltage fraction is applied to a third offset input of the comparator.
According to an embodiment, the comparator has a first high gain branch, from which the output digital signal is derived, composed by a single NMOS transistor driven by the output of the low-pass filter and electrically connected in parallel to a plurality of NMOS transistors identical to the single NMOS transistor but driven in common by the fraction of the output voltage.
The other branch of the comparator is identical to the first branch but the single NMOS transistor and the plurality of NMOS transistors are all driven in common by the constant reference voltage.